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SCSI Registers 4-61
the current DBC value. This bit automatically clears itself
after incrementing the DNAD register.
BBCK Clock Byte Counter 6
Setting this bit decrements the byte count contained in
the 24-bit DBC register. It is decremented based on the
DMA Byte Counter (DBC) contents and the current DMA
Next Address (DNAD) value. This bit automatically clears
itself after decrementing the DBC register.
DFS DMA FIFO Size 5
This bit controls the size of the DMA FIFO. When clear,
the DMA FIFO appears as only 112 bytes deep. When
set, the DMA FIFO size increases to 944 bytes. Using an
112-byte FIFO allows software written for other
LSI53C8XX family chips to properly calculate the number
of bytes residing in the chip after a target disconnect. The
default value of this bit is zero.
MASR Master Control for Set or Reset Pulses 4
This bit controls the operation of bit 3. When this bit is
set, bit 3 asserts the corresponding signals. When this bit
is cleared, bit 3 deasserts the corresponding signals. Do
not change this bit and bit 3 in the same write cycle.
DDIR DMA Direction 3
Setting this bit either asserts or deasserts the internal
DMA Write (DMAWR) direction signal depending on the
current status of the MASR bit in this register. Asserting
the internal DMA write signal indicates that data is
transferred from the SCSI bus to the host bus.
Deasserting the internal DMA write signal transfers data
from the host bus to the SCSI bus.
BL2 Burst Length Bit 2 2
This bit works with bits 6 and 7 (BL[1:0]) in the DMA
Mode (DMODE), 0x38 register to determine the burst
length. For complete definitions of this field, refer to the
descriptions of DMODE bits 6 and 7. This bit is disabled
if a 112-byte FIFO is selected by clearing the DMA FIFO
size bit.