Filter
Top Products
PCI Functional Description 2-3
2.1.1.1 Configuration Space
The host processor uses the PCI configuration space to initialize the
LSI53C875A through a defined set of configuration space registers. The
Configuration registers are accessible only by system BIOS during PCI
configuration cycles. The configuration space is a contiguous
256 X 8-bit set of addresses. Decoding C_BE[3:0]/ determines if a PCI
cycle is intended to access the configuration register space. The IDSEL
bus signal is a “chip select” that allows access to the configuration
register space only. A configuration read/write cycle without IDSEL is
ignored. The eight lower order address bits, AD[7:0], select a specific
8-bit register. AD[10:8] are decoded as well, but they must be zero or the
LSI53C875A does not respond. According to the PCI specification,
AD[10:8] are reserved for multifunction devices.
At initialization time, each PCI device is assigned a base address for I/O
and memory accesses. In the case of the LSI53C875A, the upper 24 bits
of the address are selected. On every access, the LSI53C875A
compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C875A and the low-order eight bits
define the register being accessed. A decode of C_BE[3:0]/ determines
which registers and what type of access is to be performed.
I/O Space – The PCI specification defines I/O space as a contiguous
32-bit I/O address that is shared by all system resources, including the
LSI53C875A. Base Address Register Zero (I/O) determines which
256-byte I/O area this device occupies.
Memory Space – The PCI specification defines memory space as a
contiguous 64-bit memory address that is shared by all system
resources, including the LSI53C875A. Base Address Register One
(MEMORY) determines which 1 Kbyte memory area this device
occupies. Base Address Register Two (SCRIPTS RAM) determines the
4 Kbyte memory area occupied by SCRIPTS RAM.
2.1.2 PCI Bus Commands and Functions Supported
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE[3:0]/ lines
during the address phase. PCI bus commands and encoding types
appear in Table 2.1.