Filter
Top Products
2-20 Functional Description
2.2.5 Designing an Ultra SCSI System
Since Ultra SCSI is based on existing SCSI standards, it can use existing
driver programs as long as the software is able to negotiate for Ultra
SCSI synchronous transfer rates. Additional software modifications are
needed to take advantage of the new features in the LSI53C875A.
For additional information on Ultra SCSI, refer to the SPI-2 working
document which is available from the SCSI BBS referenced at the
beginning of this manual. Chapter 6, “Electrical Specifications,” contains
Ultra SCSI timing information. In addition to the guidelines in the draft
standard, make the following software and hardware adjustments to
accommodate Ultra SCSI transfers:
• Set the Ultra Enable bit to enable Ultra SCSI transfers.
• Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3)
register, whenever the Ultra Enable bit is set.
• Do not extend the SREQ/SACK filtering period with SCSI Test Two
(STEST2) bit 1. When the Ultra Enable bit is set, the filtering period
is fixed at 15 ns for Ultra SCSI, regardless of the value of the
SREQ/SACK Filtering bit.
• Use the SCSI clock quadrupler.
A 20 or 40 MHz input must be supplied if using the SCSI clock
quadrupler for an Ultra design.
2.2.5.1 Using the SCSI Clock Quadrupler
The LSI53C875A can quadruple the frequency of a 20 MHz SCSI clock,
allowing the system to perform Ultra SCSI transfers. This option is user
selectable with bit settings in the SCSI Test One (STEST1), SCSI Test
Three (STEST3),andSCSI Control Three (SCNTL3) registers. At
power-on or reset, the quadrupler is disabled and powered down. Follow
these steps to use the clock quadrupler:
Step 1. Set the SCLK Quadrupler Enable bit (SCSI Test One
(STEST1),bit3).
Step 2. Poll bit 5 of the SCSI Test Four (STEST4) register.
The LSI53C875A sets this bit as soon as it locks in the
quadrupled frequency. The frequency lockup takes
approximately 100
µs.