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LSI53C875A Benefits Summary 1-5
• Ease of Use
• Flexibility
• Reliability
• Testability
1.4.1 SCSI Performance
To improve SCSI performance, the LSI53C875A:
• Has integrated SE transceivers.
• Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO.
• Performs wide, Ultra SCSI synchronous transfers as fast as
40 Mbytes/s.
• Can handle phase mismatches in SCRIPTS without interrupting the
system processor, eliminating the need for CPU intervention during
an I/O disconnect/reselect sequence.
• Achieve Ultra SCSI transfer rates with an input frequency of 20 MHz
with the on-chip SCSI clock quadrupler.
• Includes 4 Kbytes internal RAM for SCRIPTS instruction storage.
• Has 31 levels of SCSI synchronous offset.
• Supports variable block size and scatter/gather data transfers.
• Performs sustained memory-to-memory DMA transfers to
approximately 100 Mbytes/s.
• Minimizes SCSI I/O start latency.
• Performs complex bus sequences without interrupts, including
restoring data pointers.
• Reduces ISR overhead through a unique interrupt status reporting
method.
• Uses Load/Store SCRIPTS instructions which increase performance
of data transfers to and from the chip registers without using PCI
cycles.
• Has SCRIPTS support for 64-bit addressing.
• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.