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2-18 Functional Description
The Phase Mismatch Jump logic powers up disabled and must be
enabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, bit 7
in the Chip Control 0 (CCNTL0) register).
Utilizing the information supplied in the PhaseMismatchJumpAddress
1(PMJAD1)and Phase Mismatch Jump Address 2 (PMJAD2) registers,
described in Chapter 4, “Registers,” SCRIPTS handles all overhead
involved in a disconnect/reselect sequence with a modest number of
instructions.
2.2.2 Internal SCRIPTS RAM
The LSI53C875A has 4 Kbyte (1024 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the chip, except Load/Store, use the PCI
bus, as if they were external accesses. The SCRIPTS RAM powers up
enabled by default.
The RAM can be relocated by the PCI system BIOS anywhere in the
32-bit address space. The Base Address Register Two (SCRIPTS RAM)
in the PCI configuration space contains the base address of the internal
RAM. To simplify loading of the SCRIPTS instructions, the base address
of the RAM appears in the Scratch Register B (SCRATCHB) register
when bit 3 of the Chi p Test Two (CT EST2) register is set. The RAM is
byte accessible from the PCI bus and is visible to any bus mastering
device on the bus. External accesses to the RAM (by the CPU) follow
the same timing sequence as a standard slave register access, except
that the required target wait-states drop from 5 to 3.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C875A, see Chapter 5, “SCSI
SCRIPTS Instruction Set.”