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PCI and External Memory Interface Timing Diagrams 6-15
Figure 6.11 32-Bit Operating Register/SCRIPTS RAM Read
Table 6.17 32-Bit Operating Register/SCRIPTS RAM Read
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD
(Driven by Master-Addr;
LSI53C875A-Data)
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C875A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
CMD
Byte Enable
Data
Out
Out
In
t
1
t
2
t
3
Addr
In
t
1
t
1
t
1
t
2
t
2
t
2
t
3
t
3
t
3
t
2
t
2