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4-56 Registers
Register: 0x1B
Chip Test Three (CTEST3)
Read/Write
V ChipRevisionLevel [7:4]
These bits identify the chip revision level for software
purposes. It should have the same value as the lower
nibble of the PCI Revision ID (Rev ID) register, at address
0x08 in the configuration space.
FLF Flush DMA FIFO 3
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the DMA
Next Address 64 (DNAD64) register. The internal
DMAWR signal, controlled by the Chip Test Five
(CTEST5) register, determines the direction of the
transfer. This bit is not self-clearing; clear it once the data
is successfully transferred by the LSI53C875A.
Note:
Polling of FIFO flags is allowed during flush operations.
CLF Clear DMA FIFO 2
When this bit is set, all data pointers for the DMA FIFO
are cleared. Any data in the FIFO is lost. After the
LSI53C875A successfully clears the appropriate FIFO
pointers and registers, this bit automatically clears.
Note:
This bit does not clear the data visible at the bottom of the
FIFO.
FM Fetch Pin Mode 1
When set, this bit causes the FETCH/ pin to deassert
during indirect and table indirect read operations.
FETCH/ is only active during the opcode portion of an
instruction fetch. This allows the storage of SCRIPTS in
a PROM while data tables are stored in RAM.
If this bit is not set, FETCH/ is asserted for all bus cycles
during instruction fetches.
7 43210
V FLF CLF FM WRIE
xxxx0000