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4-50 Registers
the SCRIPTS processor is still executing a SCRIPTS
program. If this bit is set when the Interrupt Status Zero
(ISTAT0) or Interrupt Status One (ISTAT1) registers are
read they are not automatically cleared. To clear this bit,
write it to a one. The reset operation is self-clearing.
Note:
If the INTF bit is set but SIP or DIP are not set, do not
attempt to read the other chip status registers. An
Interrupt-on-the-Fly interrupt must be cleared before
servicing any other interrupts indicated by SIP or DIP.
This bit must be written to one in order to clear it after it
has been set.
SIP SCSI Interrupt Pending 1
This status bit is set when an interrupt condition is
detected in the SCSI portion of the LSI53C875A. The
following conditions cause a SCSI interrupt to occur:
• A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
• An arbitration sequence completes
• A selection or reselection time-out occurs
• The LSI53C875A is selected
• The LSI53C875A is reselected
• A SCSI gross error occurs
• An unexpected disconnect occurs
• A SCSI reset occurs
• A parity error is detected
• The handshake-to-handshake timer is expired
• The general purpose timer is expired
To determine exactly which condition(s) caused the
interrupt, read the SCSI Interrupt Status Zero (SIST0)
and SCSI Interrupt Status One (SIST1) registers.
DIP DMA Interrupt Pending 0
This status bit is set when an interrupt condition is
detected in the DMA portion of the LSI53C875A. The
following conditions cause a DMA interrupt:
• A PCI parity error is detected