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SCSI Registers 4-51
• A bus fault is detected
• An abort condition is detected
• A SCRIPTS instruction is executed in single step
mode
• A SCRIPTS interrupt instruction is executed
• An illegal instruction is detected
To determine exactly which condition(s) caused the
interrupt, read the DMA Status (DSTAT) register.
Register: 0x15
Interrupt Status One (ISTAT1)
Read/Write
R Reserved [7:3]
FLSH Flushing 2
Reading this bit monitors if the chip is currently flushing
data. If set, the chip is flushing data from the DMA FIFO.
If cleared, no flushing is occurring. This bit is read only
and writes will have no effect on the value of this bit.
SRUN SCRIPTS Running 1
This bit indicates whether or not the SCRIPTS engine is
currently fetching and executing SCRIPTS instructions. If
this bit is set, the SCRIPTS engine is active.
If it is cleared, the SCRIPTS engine is not active.
This bit is read only and writes will have no effect on the
value of this bit.
SI SYNC_IRQD 0
Setting this bit disables the IRQ/ pin. Clearing this bit
enables normal operation of the IRQ/ pin. The function of
this bit is nearly identical to bit 1 of the DMA Control
(DCNTL) (0x3B) register except that if the IRQ/ is already
asserted and this bit is set, IRQ/ will remain asserted until
the interrupt is serviced. At this point the IRQ/ line will be
blocked for future interrupts until this bit is cleared. In
7 3210
RFLSHSRUNSI
x x x x x000