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SCSI Functional Description 2-31
then the least significant byte or the most significant byte in the
SODR register is full, respectively.
Asynchronous SCSI Receive –
Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test
Five (CTEST5) register cleared), look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between zero and 88.
If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test
Five (CTEST5) register is set), subtract the 10 least significant
bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO
register. AND the result with 0x3FF for a byte count between
zero and 944.
Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status
Two (SS TAT2) registers to determine if any bytes are left in the
SCSI Input Data Latch (SIDL) register.Ifbit7issetinthe
SSTAT0 or SSTAT2 register, then the least significant byte or
the most significant byte is full, respectively.
Step 3. If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (SCSI Status
Two (SSTAT2) , bit 0) to determine whether a byte is left in the
SCSI Wide Residue (SWIDE) register.
Synchronous SCSI Receive –
Step 1. If the DMA FIFO size is set to 112 bytes, subtract the seven
least significant bits of the DMA Byte Counter (DBC) register
from the 7-bit value of the DMA FIFO (DFIFO) register. AND
the result with 0x7F for a byte count between zero and 112.
If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test
Five (CTEST5) register is set), subtract the 10 least significant
bits of the DBC register from the 10-bit value of the DMA FIFO
Byte Offset Counter, which consists of bits [1:0] in the Chip Test
Five (CTEST5) register and bits [7:0] of the DMA FIFO register.