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SCSI Registers 4-71
the LSI53C875A to make more efficient use of the
system PCI bus, thus improving overall system
performance. The unit will flush whenever the PFF bit is
set, as well as on all transfer control instructions when
the transfer conditions are met, on every write to the
DMA SCRIPTS Pointer (DSP), on every regular MMOV
instruction, and when any interrupt is generated. The unit
automatically determines the maximum burst size that it
is capable of performing based on the burst length as
determined by the values in the DMA Mode (DMODE)
register. If the burst threshold is set to 8 Dwords the
prefetch unit will fetch instructions in two bursts of
4 Dwords. If the burst threshold is set to 16 Dwords or
greater the prefetch unit will fetch instructions in one burst
of 8 Dwords. Burst thresholds of less than 8 Dwords will
cause the prefetch unit to be disabled. PCI Cache
commands (Read Line and Read Multiple) will be issued
appropriately if PCI caching is enabled. Prefetching from
SCRIPTS RAM is not supported and is unnecessary due
to the speed of the fetches. When fetching from
SCRIPTS RAM the setting of this bit will have no effect
on the fetch mechanism from SCRIPTS RAM.
SSM Single Step Mode 4
Setting this bit causes the LSI53C875A to stop after
executing each SCRIPTS instruction, and generate a
single step interrupt. When this bit is cleared the
LSI53C875A does not stop after each instruction. It
continues fetching and executing instructions until an
interrupt condition occurs. For normal SCSI SCRIPTS
operation, keep this bit clear. To restart the LSI53C875A
after it generates a SCRIPTS Step interrupt, read the
Interrupt Status Zero (ISTAT0), Interrupt Status One
(ISTAT1) and DMA Status (DSTAT) registers to recognize
and clear the interrupt. Then set the START DMA bit in
this register.
IRQM IRQ Mode 3
When set, this bit enables a totem pole driver for the IRQ/
pin. When cleared, this bit enables an open drain driver
for the IRQ/ pin with an internal weak pull-up. The bit
should remain cleared to retain full PCI compliance.