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4-90 Registers
SZM SCSI High Impedance Mode 3
Setting this bit places all the open drain 48 mA SCSI
drivers into a high impedance state. This is to allow
internal loopback mode operation without affecting the
SCSI bus.
AWS AlwaysWideSCSI 2
When this bit is set, all SCSI information transfers are
done in 16-bit wide mode. This includes data, message,
command, status and reserved phases. Normally,
deassert this bit since 16-bit wide message, command,
and status phases are not supported by the SCSI
specifications.
EXT Extend SREQ/SACK/ Filtering 1
LSI Logic TolerANT SCSI receiver technology includes a
special digital filter on the SREQ/ and SACK/ pins which
causes the disregarding of glitches on deasserting
edges. Setting this bit increases the filtering period from
30 ns to 60 ns on the deasserting edge of the SREQ/ and
SACK/ signals.
Note:
Never set this bit during fast SCSI (greater than 5 Mbyte
transfers per second) operations, because a valid assertion
could be treated as a glitch.
LOW SCSI Low level Mode 0
Setting this bit places the LSI53C875A in the low level
mode. In this mode, no DMA operations occur, and no
SCRIPTS execute. Arbitration and selection may be
performed by setting the start sequence bit as described
in the SCSI Control Zero (SCNTL0) register. SCSI bus
transfers are performed by manually asserting and polling
SCSI signals. Clearing this bit allows instructions to be
executed in SCSI SCRIPTS mode.
Note:
It is not necessary to set this bit for access to the SCSI
bit-level registers SCSI Output Data Latch (SODL), SCSI
Bus Control Lines (SBCL), and input registers.