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4-58 Registers
while data is being transferred between the two cores.
Once the chip has stopped transferring data, these bits
are stable.
The DMA FIFO (DFIFO) register counts the number of
bytes transferred between the DMA core and the SCSI
core. The DMA Byte Counter (DBC) register counts the
number of bytes transferred across the host bus. The
difference between these two counters represents the
number of bytes remaining in the DMA FIFO.
The following steps determine how many bytes are left in
the DMA FIFO when an error occurs, regardless of the
transfer direction:
If the DFS bit (bit 5, Chip Test Five (CTEST5))isset:
1. Subtract the ten least significant bits of the DMA
Byte Counter (DBC) register from the 10-bit value of
the DFBOC. The DFBOC consists of the Chip Test
Five (CTEST5) register, bits 1 and 0 and the DMA
FIFO (DFIFO) register, bits [7:0].
2. AND the result with 0x3FF for a byte count between
zero and 944.
If the DFS bit (bit 5, Chip Test Five (CTEST5)) is cleared:
1. Subtract the seven least significant bits of the DMA
Byte Counter (DBC) register from the seven bit value
oftheDFBOCwhichismadeupoftheDMA FIFO
(DFIFO) register, bits [6:0].
2. AND the result with 0x7F for a byte count between
zero and 112.
Note:
If trying to calculate the total number of bytes in both the
DMA FIFO and SCSI Logic, see Section2.2.12.1“Data
Paths” in Chapter 2, “Functional Description.”