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PCI and External Memory Interface Timing Diagrams 6-13
6.4.1 Target Timing
The tables and figures in this section describe target timings.
Figure 6.9 PCI Configuration Register Read
Table 6.15 PCI Configuration Register Read
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
CLK
FRAME/
AD
(Driven by Master-Addr;
LSI53C875A-Data)
C_BE/
(Driven by Master
)
PAR
(Driven by Master-Addr;
LSI53C875A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875A)
STOP/
(Driven by LSI53C875A)
DEVSEL/
(Driven by LSI53C875A)
IDSEL
(Driven by Master)
t
1
t
2
Data Out
Byte Enable
t
1
t
1
t
1
t
2
t
1
t
2
t
2
t
2
t
1
t
2
t
2
t3
t
3
t
3
t
3
OutIn
Addr
In
(Driven by System)
(Driven by System)
CMD