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Instruction Set
3-70
RISC 16−Bit CPU
* TST[.W] Test destination
* TST.B Test destination
Syntax TST dst or TST.W dst
TST.B dst
Operation dst + 0FFFFh + 1
dst + 0FFh + 1
Emulation CMP #0,dst
CMP.B #0,dst
Description The destination operand is compared with zero. The status bits are set accord-
ing to the result. The destination is not affected.
Status Bits N: Set if destination is negative, reset if positive
Z: Set if destination contains zero, reset otherwise
C: Set
V: Reset
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero,
continue at R7POS.
TST R7 ; Test R7
JN R7NEG ; R7 is negative
JZ R7ZERO ; R7 is zero
R7POS ...... ; R7 is positive but not zero
R7NEG ...... ; R7 is negative
R7ZERO ...... ; R7 is zero
Example The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive
but not zero, continue at R7POS.
TST.B R7 ; Test low byte of R7
JN R7NEG ; Low byte of R7 is negative
JZ R7ZERO ; Low byte of R7 is zero
R7POS ...... ; Low byte of R7 is positive but not zero
R7NEG ..... ; Low byte of R7 is negative
R7ZERO ...... ; Low byte of R7 is zero