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USART Operation: SPI Mode
14-10
USART Peripheral Interface, SPI Mode
Serial Clock Polarity and Phase
The polarity and phase of UCLK are independently configured via the CKPL
and CKPH control bits of the USART. Timing for each case is shown in
Figure 14−9.
Figure 14−9. USART SPI Timing
CKPH CKPL
Cycle#
UCLK
UCLK
UCLK
UCLK
SIMO/
SOMI
SIMO/
SOMI
Move to UxTXBUF
RX Sample Points
0
1
0
0
01
11
0X
1X
MSB
MSB
12345678
LSB
LSB
TX Data Shifted Out
STE