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ADC12 Operation
17-10
ADC12
17.2.6 Conversion Memory
There are 16 ADC12MEMx conversion memory registers to store conversion
results. Each ADC12MEMx is configured with an associated ADC12MCTLx
control register. The SREFx bits define the voltage reference and the INCHx
bits select the input channel. The EOS bit defines the end of sequence when
a sequential conversion mode is used. A sequence rolls over from
ADC12MEM15 to ADC12MEM0 when the EOS bit in ADC12MCTL15 is not
set.
The CSTARTADDx bits define the first ADC12MCTLx used for any
conversion. If the conversion mode is single-channel or repeat-single-channel
the CSTARTADDx points to the single ADC12MCTLx to be used.
If the conversion mode selected is either sequence-of-channels or
repeat-sequence-of-channels, CSTARTADDx points to the first
ADC12MCTLx location to be used in a sequence. A pointer, not visible to
software, is incremented automatically to the next ADC12MCTLx in a
sequence when each conversion completes. The sequence continues until an
EOS bit in ADC12MCTLx is processed - this is the last control byte processed.
When conversion results are written to a selected ADC12MEMx, the
corresponding flag in the ADC12IFGx register is set.
17.2.7 ADC12 Conversion Modes
The ADC12 has four operating modes selected by the CONSEQx bits as
discussed in Table 17−1.
Table 17−1.Conversion Mode Summary
CONSEQx Mode Operation
00 Single channel
single-conversion
A single channel is converted once.
01 Sequence-of-
channels
A sequence of channels is converted once.
10 Repeat-single-
channel
A single channel is converted repeatedly.
11
Repeat-sequence-
of-channels
A sequence of channels is converted
repeatedly.