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8.2.9 Using the I
2
C Module with the DMA Controller
The I
2
C module provides two trigger sources for the DMA controller. The I
2
C
module can trigger a transfer when new I
2
C data is received and the when the
transmit data is needed.
The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA
controller with the I
2
C module. When RXDMAEN = 1, the DMA controller can
be used to transfer data from the I
2
C module after the I
2
C modules receives
data. When RXDMAEN = 1, RXRDYIE is ignored and RXRDYIFG will not
generate an interrupt.
When TXDMAEN = 1, the DMA controller can be used to transfer data to the
I
2
C module for transmission. When TXDMAEN = 1, TXRDYIE is ignored and
TXRDYIFG will not generate an interrupt.
8.2.10 Using ADC12 with the DMA Controller
MSP430 devices with an integrated DMA controller can automatically move
data from any ADC12MEMx register to another location. DMA transfers are
done without CPU intervention and independently of any low-power modes.
The DMA controller increases throughput of the ADC12 module, and
enhances low-power applications allowing the CPU to remain off while data
transfers occur.
DMA transfers can be triggered from any ADC12IFGx flag. When CONSEQx
= {0,2} the ADC12IFGx flag for the ADC12MEMx used for the conversion can
trigger a DMA transfer. When CONSEQx = {1,3}, the ADC12IFGx flag for the
last ADC12MEMx in the sequence can trigger a DMA transfer. Any
ADC12IFGx flag is automatically cleared when the DMA controller accesses
the corresponding ADC12MEMx.
8.2.11 Using DAC12 With the DMA Controller
MSP430 devices with an integrated DMA controller can automatically move
data to the DAC12_xDAT register. DMA transfers are done without CPU
intervention and independently of any low-power modes. The DMA controller
increases throughput to the DAC12 module, and enhances low-power
applications allowing the CPU to remain off while data transfers occur.
Applications requiring periodic waveform generation can benefit from using
the DMA controller with the DAC12. For example, an application that produces
a sinusoidal waveform may store the sinusoid values in a table. The DMA
controller can continuously and automatically transfer the values to the DAC12
at specific intervals creating the sinusoid with zero CPU execution. The
DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA
controller accesses the DAC12_xDAT register.