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Timer_A Introduction
11-3
Timer_A
Figure 11−1. Timer_A Block Diagram
Compararator 2
CCI
15 0
CCISx
OUTMODx
Capture
Mode
CMx
Sync
SCS
COVlogic
Output
Unit2
D
Set
Q
EQU0
OUT
OUT2 Signal
Reset
GND
VCC
CCI2A
CCI2B
EQU2
Divider
1/2/4/8
Count
Mode
16−bit Timer
TAR
RC
ACLK
SMCLK
TACLK
INCLK
Set TAIFG
15 0
TASSELx
MCxIDx
00
01
10
11
Clear
Timer Clock
EQU0
Timer Clock
Timer Clock
SCCI Y
A
EN
CCR1
POR
TACLR
CCR0
Timer Block
00
01
10
11
CAP
1
0
1
0
CCR2
Set TACCR2
CCIFG
TACCR2