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ADC10 Introduction
18-3
ADC10
Figure 18−1. ADC10 Block Diagram
1001
1000
0010
0001
0011
0100
0101
0110
0111
Sample
and
Hold
10−bit SAR
Divider
/1 .. /8
ACLK
MCLK
SMCLK
ADC10SC
TA1
TA2
TA0
Data Transfer
Controller
RAM, Flash, Peripherials
V
R−
V
R+
Ve
REF+
V
REF+
Ve
REF−
V
REF−
/
ADC10ON
INCHx
REFBURST
ADC10SSELx
ADC10DIVx
SHSx
ADC10SHTx
MSC
ENC
BUSY
ADC10DF
ADC10CLK
SREF2
ADC10TB ADC10B1ADC10CT
ISSH
ADC10SR
ADC10OSC
Ref_x
S/H
Convert
SAMPCON
1
0
Sync
Sample Timer
/4/8/16/64
SHI
ADC10SA
n
4
A0
A1
A2
A3
A4
A5
A6
A7
REFON
INCHx=0Ah
1.5 V or 2.5 V
Reference
on
Ref_x
SREF1
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
000111
01
SREF0
1011
REFOUT
1010
10
CONSEQx
1
0
INCHx=0Bh
Auto
ADC10MEM
R
R
0001
1111
1110
1101
1100
0000
Halt CPU
REF2_5V
V
CC
V
CC
V
SS
V
SS
V
CC