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I
2
C Module Registers
15-26
USART Peripheral Interface, I
2
C Mode
I2CSCLH, I
2
C Shift Clock High Register
76543210
I2CSCLHx
rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0
Modifiable only when I2CEN = 0
I2CSCLHx
Bits
7−0
I
2
C shift clock high. These bits define the high period of SCL when the I
2
C
controller is in master mode. The SCL high period is (I2CSCLH+2) x (I2CPSC
+ 1).
000h SCL high period = 5 x (I2CPSC + 1)
001h SCL high period = 5 x (I2CPSC + 1)
002h SCL high period = 5 x (I2CPSC + 1)
003h SCL high period = 5 x (I2CPSC + 1)
004h SCL high period = 6 x (I2CPSC + 1)
:
0FFh SCL high period = 257 x (I2CPSC + 1)
I2CSCLL, I
2
C Shift Clock Low Register
76543210
I2CSCLLx
rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0
Modifiable only when I2CEN = 0
I2CSCLLx
Bits
7−0
I
2
C shift clock low. These bits define the low period of SCL when the I
2
C
controller is in master mode. The SCL low period is (I2CSCLL+2) x (I2CPSC
+ 1).
000h SCL low period = 5 x (I2CPSC + 1)
001h SCL low period = 5 x (I2CPSC + 1)
002h SCL low period = 5 x (I2CPSC + 1)
003h SCL low period = 5 x (I2CPSC + 1)
004h SCL low period = 6 x (I2CPSC + 1)
:
0FFh SCL low period = 257 x (I2CPSC + 1)