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Timer_B Registers
12-22
Timer_B
Unused
Bit 3 Unused
TBCLR
Bit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the count
direction. The TBCLR bit is automatically reset and is always read as zero.
TBIE
Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request.
0 Interrupt disabled
1 Interrupt enabled
TBIFG
Bit 0 Timer_B interrupt flag.
0 No interrupt pending
1 Interrupt pending
TBR, Timer_B Register
15 14 13 12 11 10 9 8
TBRx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
76543210
TBRx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
TBRx Bits
15-0
Timer_B register. The TBR register is the count of Timer_B.