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Timer_B Introduction
12-3
Timer_B
Figure 12−1. Timer_B Block Diagram
CCR6
Compararator 6
CCI
15 0
OUTMODx
Capture
Mode
CMx
Sync
COVlogic
Output
Unit6
D
Set
Q
EQU0
OUT
OUT6 Signal
Reset
POR
EQU6
Divider
1/2/4/8
Count
Mode
16−bit Timer
TBR
Set TBIFG
15 0
MCxIDx
Clear
TBCLR
Timer Clock
CCR0
EQU0
Timer Clock
Timer Clock
VCC
TBR=0
UP/DOWN
EQU0
CLLDx
CNTLx
Load
CCR1
CCR2
CCR3
CCR4
CCR5
Timer Block
TBCCR6
RC
10 12 168
TBCLGRPx
CCR5
CCR4
CCR1
Group
Load Logic
Group
Load Logic
TBSSELx
00
01
10
11
GND
VCC
CCI6A
CCI6B
00
01
10
11
CCISx
00
01
10
11
00
01
10
11
CAP
1
0
SCS
1
0
Set TBCCR6
CCIFG
Compare Latch TBCL6
ACLK
SMCLK
TBCLK