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I
2
C Module Operation
15-8
USART Peripheral Interface, I
2
C Mode
15.2.4 I
2
C Module Operating Modes
The I
2
C module operates in master transmitter, master receiver, slave
transmitter, or slave receiver mode.
Master Mode
In master mode, transmit and receive operation is controlled with the I2CRM,
I2CSTT, and I2CSTP bits as described in Table 15−1. The master transmitter
and master receiver modes are shown in Figure 15−8 and Figure 15−9. SCL
is held low when the intervention of the CPU is required after a byte has been
received or transmitted.
Table 15−1.Master Operation
I2CRM I2CSTP I2CSTT Condition Or Bus Activity
X 0 0 The I
2
C module is in master mode, but is idle. No
START or STOP condition is generated.
0 0 1 Setting I2CSTT initiates activity. I2CNDAT is used to
determine length of transmission. A STOP condition is
not automatically generated after the I2CNDAT
number of bytes have been transferred. Software must
set I2CSTP to generate a STOP condition at the end
of transmission. This is used for RESTART conditions.
0 1 1 I2CNDAT is used to determine length of transmission.
Setting I2CSTT initiates activity. A STOP condition is
automatically generated after I2CNDAT number of
bytes have been transferred.
1 0 1 I2CNDAT is not used to determine length of
transmission. Software must control the length of the
transmission. Setting the I2CSTT bit initiates activity.
Software must set the I2CSTP bit to initiate a STOP
condition and stop activity. This mode is useful if > 255
bytes are to be transferred.
0 1 0 Setting the I2CSTP bit generates a STOP condition on
the bus after I2CNDAT number of bytes have been
sent, or immediately if I2CNDAT number of bytes have
already been sent.
1 1 0 Setting the I2CSTP bit generates a STOP condition on
the bus after the current transmission completes, or
immediately if no transmission is currently active.
1 1 1 Reserved, no bus activity.