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Timer_A Operation
11-4
Timer_A
11.2 Timer_A Operation
The Timer_A module is configured with user software. The setup and
operation of Timer_A is discussed in the following sections.
11.2.1 16-Bit Timer Counter
The 16-bit timer/counter register, TAR, increments or decrements (depending
on mode of operation) with each rising edge of the clock signal. TAR can be
read or written with software. Additionally, the timer can generate an interrupt
when it overflows.
TAR may be cleared by setting the TACLR bit. Setting TACLR also clears the
clock divider and count direction for up/down mode.
Note: Modifying Timer_A Registers
It is recommended to stop the timer before modifying its operation (with
exception of the interrupt enable, interrupt flag, and TACLR) to avoid errant
operating conditions.
When the TACLK is asynchronous to the CPU clock, any read from TAR
should occur while the timer is not operating or the results may be
unpredictable. Alternatively, the timer may be read multiple times while
operating, and a majority vote taken in software to determine the correct
reading. Any write to TAR will take effect immediately.
Clock Source Select and Divider
The timer clock TACLK can be sourced from ACLK, SMCLK, or externally via
TACLK or INCLK. The clock source is selected with the TASSELx bits. The
selected clock source may be passed directly to the timer or divided by 2, 4,
or 8, using the IDx bits. The TACLK divider is reset when TACLR is set.