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ADC12 Registers
17-24
ADC12
ADC12
SSELx
Bits
4-3
ADC12 clock source select
00 ADC12OSC
01 ACLK
10 MCLK
11 SMCLK
CONSEQx
Bits
2-1
Conversion sequence mode select
00 Single-channel, single-conversion
01 Sequence-of-channels
10 Repeat-single-channel
11 Repeat-sequence-of-channels
ADC12
BUSY
Bit 0 ADC12 busy. This bit indicates an active sample or conversion operation.
0 No operation is active.
1 A sequence, sample, or conversion is active.
ADC12MEMx, ADC12 Conversion Memory Registers
15 14 13 12 11 10 9 8
0
0 0 0 Conversion Results
r0 r0 r0 r0 rw rw rw rw
76543210
Conversion Results
rw rw rw rw rw rw rw rw
Conversion
Results
Bits
15-0
The 12-bit conversion results are right-justified. Bit 11 is the MSB. Bits 15-12
are always 0. Writing to the conversion memory registers will corrupt the
results.