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8-7
Figure 8−3. DMA Single Transfer State Diagram
Reset
Wait for Trigger
Idle
Hold CPU,
Transfer one word/byte
[+Trigger AND DMALEVEL = 0 ]
OR
[Trigger=1 AND DMALEVEL=1]
DMAABORT=0
DMAABORT = 1
2 x MCLK
DMAEN = 0
Modify T_SourceAdd
Modify T_DestAdd
Decrement DMAxSZ
[ENNMI = 1
AND NMI event]
OR
[DMALEVEL = 1
AND Trigger = 0]
[ DMADTx = 0
AND DMAxSZ = 0]
OR DMAEN = 0
DMAxSZ → T_Size
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
DMAREQ = 0
DMAxSZ > 0
AND DMAEN = 1
DMAEN = 0
DMAEN = 1
T_Size → DMAxSZ
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
DMADTx = 4
AND DMAxSZ = 0
AND DMAEN = 1
DMAEN = 0
DMAREQ = 0
T_Size → DMAxSZ