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Instruction Set
3-32
RISC 16−Bit CPU
* CLRN Clear negative bit
Syntax CLRN
Operation 0 → N
or
(.NOT.src .AND. dst −> dst)
Emulation BIC #4,SR
Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the
destination operand. The result is placed into the destination. The clear
negative bit instruction is a word instruction.
Status Bits N: Reset to 0
Z: Not affected
C: Not affected
V: Not affected
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example The Negative bit in the status register is cleared. This avoids special treatment
with negative numbers of the subroutine called.
CLRN
CALL SUBR
......
......
SUBR JN SUBRET ; If input is negative: do nothing and return
......
......
......
SUBRET RET