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8-3
Figure 8−1. DMA Controller Block Diagram
DMA Priority And Control
ENNMI
DT
DMA Channel 2
DMASRSBYTE
DMA2SZ
DMA2DA
DMA2SA
DMADSTBYTE
DMASRCINCRx
DMADSTINCRx
2
2
3
DMADTx
DMAEN
DT
DMA Channel 1
DMASRSBYTE
DMA1SZ
DMA1DA
DMA1SA
DMADSTBYTE
DMASRCINCRx
DMADSTINCRx
2
2
3
DMADTx
DMAEN
DT
DMA Channel 0
DMASRSBYTE
DMA0SZ
DMA0DA
DMA0SA
DMADSTBYTE
DMASRCINCRx
DMADSTINCRx
2
2
3
DMADTx
DMAEN
Address
Space
NMI Interrupt Request
JTAG Active
Halt
Halt CPU
ROUNDROBIN
DMAONFETCH
DAC12_0IFG
DMAE0
DMAREQ
DMA0TSELx
4
DMA2IFG
TACCR2_CCIFG
TBCCR2_CCIFG
USART0 data received
USART0 transmit ready
USART1 transmit ready
USART1 data received
DMAE0
4
DMA0IFG
0000
0001
0010
0011
0100
0101
−−−
1111
1110
0110
0111
1000
1001
1010
DMAE0
4
DMA1IFG
0000
0001
0010
0011
0100
0101
−−−
1111
1110
0110
0111
1000
1001
1010
0000
0001
0010
0011
0100
0101
−−−
1111
1110
0110
0111
1000
1001
1010
Multiplier ready
No trigger
No trigger
DAC12_0IFG
DMAREQ
TACCR2_CCIFG
TBCCR2_CCIFG
USART0 data received
USART0 transmit ready
USART1 transmit ready
USART1 data received
Multiplier ready
No trigger
No trigger
DAC12_0IFG
DMAREQ
TACCR2_CCIFG
TBCCR2_CCIFG
USART0 data received
USART0 transmit ready
USART1 transmit ready
USART1 data received
Multiplier ready
No trigger
No trigger
1011
1011
1011
DMA1TSELx
DMA2TSELx
TACCR0_CCIFG
TBCCR0_CCIFG
TACCR0_CCIFG
TBCCR0_CCIFG
TACCR0_CCIFG
TBCCR0_CCIFG
ADC12IFGx
ADC12IFGx
ADC12IFGx