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ADC10 Registers
18-31
ADC10
ADC10DTC1, Data Transfer Control Register 1
76543210
DTC Transfers
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
DTC
Transfers
Bits
7-0
DTC transfers. These bits define the number of transfers in each block.
0 DTC is disabled
01h-0FFh Number of transfers per block
ADC10SA, Start Address Register for Data Transfer
15 14 13 12 11 10 9 8
ADC10SAx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(1) rw−(0)
76543210
ADC10SAx 0
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r0
ADC10SAx
Bits
15-1
ADC10 start address. These bits are the start address for the DTC. A write
to register ADC10SA is required to initiate DTC transfers.
Unused
Bit 0 Unused, Read only. Always read as 0.