Filter
Top Products
Instruction Set
3-17
RISC 16-Bit CPU
3.4 Instruction Set
The complete MSP430 instruction set consists of 27 core instructions and 24
emulated instructions. The core instructions are instructions that have unique
op-codes decoded by the CPU. The emulated instructions are instructions that
make code easier to write and read, but do not have op-codes themselves,
instead they are replaced automatically by the assembler with an equivalent
core instruction. There is no code or performance penalty for using emulated
instruction.
There are three core-instruction formats:
- Dual-operand
- Single-operand
- Jump
All single-operand and dual-operand instructions can be byte or word
instructions by using .B or .W extensions. Byte instructions are used to access
byte data or byte peripherals. Word instructions are used to access word data
or word peripherals. If no extension is used, the instruction is a word
instruction.
The source and destination of an instruction are defined by the following fields:
src The source operand defined by As and S-reg
dst The destination operand defined by Ad and D-reg
As The addressing bits responsible for the addressing mode used
for the source (src)
S-reg The working register used for the source (src)
Ad The addressing bits responsible for the addressing mode used
for the destination (dst)
D-reg The working register used for the destination (dst)
B/W Byte or word operation:
0: word operation
1: byte operation
Note: Destination Address
Destination addresses are valid anywhere in the memory map. However,
when using an instruction that modifies the contents of the destination, the
user must ensure the destination address is writable. For example, a
masked-ROM location would be a valid destination address, but the contents
are not modifiable, so the results of the instruction would be lost.