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DMACTL0, DMA Control Register 0
15 14 13 12 11 10 9 8
Reserved DMA2TSELx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
76543210
DMA1TSELx DMA0TSELx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
Reserved
Bits
15−12
Reserved
DMA2
TSELx
Bits
11−8
DMA trigger select. These bits select the DMA transfer trigger.
0000 DMAREQ bit (software trigger)
0001 TACCR2 CCIFG bit
0010 TBCCR2 CCIFG bit
0011 URXIFG0 (UART/SPI mode), USART0 data received (I
2
C mode)
0100 UTXIFG0 (UART/SPI mode), USART0 transmit ready (I
2
C mode)
0101 DAC12_0CTL DAC12IFG bit
0110 ADC12 ADC12IFGx bit
0111 TACCR0 CCIFG bit
1000 TBCCR0 CCIFG bit
1001 URXIFG1 bit
1010 UTXIFG1 bit
1011 Multiplier ready
1100 No action
1101 No action
1110 DMA0IFG bit triggers DMA channel 1
DMA1IFG bit triggers DMA channel 2
DMA2IFG bit triggers DMA channel 0
1111 External trigger DMAE0
DMA1
TSELx
Bits
7−4
Same as DMA2TSELx
DMA0
TSELx
Bits
3–0
Same as DMA2TSELx