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I
2
C Module Operation
15-19
USART Peripheral Interface, I
2
C Mode
I2CIV, Interrupt Vector Generator
The I
2
C interrupt flags are prioritized and combined to source a single interrupt
vector. The interrupt vector register I2CIV is used to determine which flag
requested an interrupt. The highest priority enabled interrupt generates a
number in the I2CIV register that can be evaluated or added to the program
counter to automatically enter the appropriate software routine. Disabled I
2
C
interrupts do not affect the I2CIV value. When RXDMAEN = 1, RXRDYIFG will
not affect the I2CIV value and when TXDMAEN = 1, TXRDYIFG will not affect
the I2CIV value, regardless of the state of RXRDYIE or TXRDYIE.
Any access, read or write, of the I2CIV register automatically resets the highest
pending interrupt flag. If another interrupt flag is set, another interrupt is
immediately generated after servicing the initial interrupt.
I2CIV Software Example
The following software example shows the recommended use of I2CIV. The
I2CIV value is added to the PC to automatically jump to the appropriate routine.
I2C_ISR
ADD &I2CIV, PC ; Add offset to jump table
RETI ; Vector 0: No interrupt
JMP ALIFG_ISR ; Vector 2: ALIFG
JMP NACKIFG_ISR ; Vector 4: NACKIFG
JMP OAIFG_ISR ; Vector 6: OAIFG
JMP ARDYIFG_ISR ; Vector 8: ARDYIFG
JMP RXRDYIFG_ISR ; Vector 10: RXRDYIFG
JMP TXRDYIFG_ISR ; Vector 12: TXRDYIFG
JMP GCIFG_ISR ; Vector 14: GCIFG
STTIFG_ISR ; Vector 16
... ; Task starts here
RETI ; Return
ALIFG_ISR ; Vector 2
... ; Task starts here
RETI ; Return
NACKIFG_ISR ; Vector 4
... ; Task starts here
RETI ; Return
OAIFG_ISR ; Vector 6
... ; Task starts here
RETI ; Return
ARDYIFG_ISR ; Vector 8
... ; Task starts here
RETI ; Return
RXRDYIFG_ISR ; Vector 10
... ; Task starts here
RETI ; Return
TXRDYIFG_ISR ; Vector 12
... ; Task starts here
RETI ; Return
GCIFG_ISR ; Vector 14
... ; Task starts here
RETI ; Return