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I
2
C Module Operation
15-14
USART Peripheral Interface, I
2
C Mode
Figure 15−12. Slave Receiver
IDLE
I2CBB Is Cleared
4 x I2CPSC
Yes
Receive Data
Low Byte
From Master
RESTART
Detected ?
Send
Acknowledge
Receive Data
High Byte
From Master
Send
Acknowledge
1 x SCL
1 x SCL
8 x SCL
8 x SCL
No
I2CWORD=0
Byte Mode
STTIFG Is Set
I2CBUSY Is Set
START
Detected?
I2CBB Is Set
4 x I2CPSC
IDLE
OAIFG Set If Not
RESTART
No
Yes
Yes
No
Stop State?
I2CBUSY Is
Cleared
1 x I2CPSC
1
From Slave
Transmit Mode
Send
Acknowledge
1 x SCL
8 x SCL
Receive Slave
Address Bits 9−8
with R/W = 0
8 x SCL
Receive Slave
Address Bits 7−0
8 x SCL
Send
Acknowledge
1 x SCL
Send
Acknowledge
1 x SCL
XA = 0
2
Matched I2COA
No
Match
No
Match
XA = 1
Matched I2COA
Matched I2COA
No
Match
2
Receive Slave
Address Bits 6−0
with R/W = 0