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ADC10 Registers
18-26
ADC10
MSC
Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.
0 The sampling requires a rising edge of the SHI signal to trigger each
sample-and-conversion.
1 The first rising edge of the SHI signal triggers the sampling timer, but
further sample-and-conversions are performed automatically as soon
as the prior conversion is completed
REF2_5V
Bit 6 Reference-generator voltage. REFON must also be set.
0 1.5 V
1 2.5 V
REFON
Bit 5 Reference generator on
0 Reference off
1 Reference on
ADC10ON
Bit 4 ADC10 on
0 ADC10 off
1 ADC10 on
ADC10IE
Bit 3 ADC10 interrupt enable
0 Interrupt disabled
1 interrupt enabled
ADC10IFG
Bit 2 ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion
result. It is automatically reset when the interrupt request is accepted, or it may
be reset by software. When using the DTC this flag is set when a block of
transfers is completed.
0 No interrupt pending
1 Interrupt pending
ENC
Bit 1 Enable conversion
0 ADC10 disabled
1 ADC10 enabled
ADC10SC
Bit 0 Start conversion. Software-controlled sample-and-conversion start.
ADC10SC and ENC may be set together with one instruction. ADC10SC is
reset automatically.
0 No sample-and-conversion start
1 Start sample-and-conversion