Filter
Top Products
Instruction Set
3-39
RISC 16−Bit CPU
* DINT Disable (general) interrupts
Syntax DINT
Operation 0 → GIE
or
(0FFF7h .AND. SR → SR / .NOT.src .AND. dst −> dst)
Emulation BIC #8,SR
Description All interrupts are disabled.
The constant 08h is inverted and logically ANDed with the status register (SR).
The result is placed into the SR.
Status Bits Status bits are not affected.
Mode Bits GIE is reset. OSCOFF and CPUOFF are not affected.
Example The general interrupt enable (GIE) bit in the status register is cleared to allow
a nondisrupted move of a 32-bit counter. This ensures that the counter is not
modified during the move by any interrupt.
DINT ; All interrupt events using the GIE bit are disabled
NOP
MOV COUNTHI,R5 ; Copy counter
MOV COUNTLO,R6
EINT ; All interrupt events using the GIE bit are enabled
Note: Disable Interrupt
If any code sequence needs to be protected from interruption, the DINT
should be executed at least one instruction before the beginning of the
uninterruptible sequence, or should be followed by a NOP instruction.