Filter
Top Products
ADC10 Operation
18-4
ADC10
18.2 ADC10 Operation
The ADC10 module is configured with user software. The setup and operation
of the ADC10 is discussed in the following sections.
18.2.1 10-Bit ADC Core
The ADC core converts an analog input to its 10-bit digital representation and
stores the result in the ADC10MEM register. The core uses two
programmable/selectable voltage levels (V
R+
and V
R−
) to define the upper and
lower limits of the conversion. The digital output (N
ADC
) is full scale (03FFh)
when the input signal is equal to or higher than V
R+
, and zero when the input
signal is equal to or lower than V
R−
. The input channel and the reference
voltage levels (V
R+
and V
R−
) are defined in the conversion-control memory.
Conversion results may be in straight binary format or 2s-complement format.
The conversion formula for the ADC result when using straight binary format
is:
N
ADC
+ 1023
Vin–V
R–
V
R)
–V
R–
The ADC10 core is configured by two control registers, ADC10CTL0 and
ADC10CTL1. The core is enabled with the ADC10ON bit. With few exceptions
the ADC10 control bits can only be modified when ENC = 0. ENC must be set
to 1 before any conversion can take place.
Conversion Clock Selection
The ADC10CLK is used both as the conversion clock and to generate the
sampling period. The ADC10 source clock is selected using the ADC10SSELx
bits and can be divided from 1-8 using the ADC10DIVx bits. Possible
ADC10CLK sources are SMCLK, MCLK, ACLK and an internal oscillator
ADC10OSC .
The ADC10OSC, generated internally, is in the 5-MHz range, but varies with
individual devices, supply voltage, and temperature. See the device-specific
datasheet for the ADC10OSC specification.
The user must ensure that the clock chosen for ADC10CLK remains active
until the end of a conversion. If the clock is removed during a conversion, the
operation will not complete, and any result will be invalid.