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8.2.6 DMA Transfer Cycle Time
The DMA controller requires one or two MCLK clock cycles to synchronize
before each single transfer or complete block or burst-block transfer. Each
byte/word transfer requires two MCLK cycles after synchronization, and one
cycle of wait time after the transfer. Because the DMA controller uses MCLK,
the DMA cycle time is dependent on the MSP430 operating mode and clock
system setup.
If the MCLK source is active, but the CPU is off, the DMA controller will use the
MCLK source for each transfer, without re-enabling the CPU. If the MCLK
source is off, the DMA controller will temporarily restart MCLK, sourced with
DCOCLK, for the single transfer or complete block or burst-block transfer. The
CPU remains off, and after the transfer completes, MCLK is turned off. The
maximum DMA cycle time for all operating modes is shown in Table 8−3.
Table 8−3.Maximum Single-Transfer DMA Cycle Time
CPU Operating Mode Clock Source Maximum DMA Cycle Time
Active mode MCLK=DCOCLK 4 MCLK cycles
Active mode MCLK=LFXT1CLK 4 MCLK cycles
Low-power mode LPM0/1 MCLK=DCOCLK 5 MCLK cycles
Low-power mode LPM3/4 MCLK=DCOCLK 5 MCLK cycles + 6 µs
†
Low-power mode LPM0/1 MCLK=LFXT1CLK 5 MCLK cycles
Low-power mode LPM3 MCLK=LFXT1CLK 5 MCLK cycles
Low-power mode LPM4 MCLK=LFXT1CLK
5 MCLK cycles + 6 µs
†
†
The additional 6 µs are needed to start the DCOCLK. It is the t
(LPMx)
parameter in the data sheet.