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Basic Clock Module Operation
4-13
Basic Clock Module
4.2.7 Synchronization of Clock Signals
When switching MCLK or SMCLK from one clock source to the another, the
switch is synchronized to avoid critical race conditions as shown in
Figure 4−11:
1) The current clock cycle continues until the next rising edge.
2) The clock remains high until the next rising edge of the new clock.
3) The new clock source is selected and continues with a full high period.
Figure 4−11. Switch MCLK from DCOCLK to LFXT1CLK
DCOCLK
LFXT1CLK
MCLK
LFXT1CLK
DCOCLK
Select
LFXT1CLK
Wait for
LFXT1CLK