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I
2
C Module Operation
15-9
USART Peripheral Interface, I
2
C Mode
Figure 15−8. Master Transmitter Mode
IDLE
Generate START
I2CBUSY Is Set
4 x I2CPSC
I2CBB Is Set
I2CSTT Is Cleared
8 x I2CPSC
Send Slave
Address Bits 6−0
with R/W=0
8 x SCL
1
Send Slave Address
Bits 9−8 Extended
with R/W = 0
8 x SCL
I2CDR Loaded?*STOP State?
STOP State?
I2CNDAT
Number Of Bytes
Sent?
Repeat Mode?
Generate STOP
10 x I2CPSC
I2CBB Is Cleared
8 x I2CPSC
I2CSTP, I2CMST
Are Cleared
8 x I2CPSC
New START?
Send I2CDR
Low Byte
8 x SCL
Send I2CDR
High Byte
8 x SCL
New START?
2
1
2
1
NACKIFG Is Set
3
XA=0
I2CRM=1
I2CRM=0
No
No
I2CDR Written
Ack
Ack, and
I2CWORD=0
Ack
No Ack
No Ack
Yes
No
Yes
I2CSTT=1
I2CDR Empty
Yes
Yes I2CSTP=1
No
3
Yes
No
*When I2RM=1, I2CSTP must be set before the last I2CDR value
is written. Othwerwise, correct STOP generation will not occur.
Send Slave Address
Bits 7−0
8 x SCL
XA=1
No ACK
No Ack
Ack
Ack
IDLE
I2CBUSY Is Cleared
IDLE
I2CBUSY Is Cleared