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ADC10 Operation
18-7
ADC10
18.2.5 Sample and Conversion Timing
An analog-to-digital conversion is initiated with a rising edge of sample input
signal SHI. The source for SHI is selected with the SHSx bits and includes the
following:
- The ADC10SC bit
- The Timer_A Output Unit 1
- The Timer_A Output Unit 0
- The Timer_A Output Unit 2
The polarity of the SHI signal source can be inverted with the ISSH bit. The
SHTx bits select the sample period t
sample
to be 4, 8, 16, or 64 ADC10CLK
cycles. The sampling timer sets SAMPCON high for the selected sample
period after synchronization with ADC10CLK.
Total sampling time is t
sample
plus t
sync
.The high-to-low SAMPCON transition starts the analog-to-digital
conversion, which requires 13 ADC10CLK cycles as shown in Figure 18−3.
Figure 18−3. Sample Timing
Start
Sampling
Stop
Sampling
Conversion
Complete
SAMPCON
SHI
t
sample
t
convert
t
sync
13 x ADC10CLKs
Start
Conversion
ADC10CLK