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Timer_B Operation
12-18
Timer_B
12.2.6 Timer_B Interrupts
Two interrupt vectors are associated with the 16-bit Timer_B module:
- TBCCR0 interrupt vector for TBCCR0 CCIFG
- TBIV interrupt vector for all other CCIFG flags and TBIFG
In capture mode, any CCIFG flag is set when a timer value is captured in the
associated TBCCRx register. In compare mode, any CCIFG flag is set when
TBR counts to the associated TBCLx value. Software may also set or clear any
CCIFG flag. All CCIFG flags request an interrupt when their corresponding
CCIE bit and the GIE bit are set.
TBCCR0 Interrupt Vector
The TBCCR0 CCIFG flag has the highest Timer_B interrupt priority and has
a dedicated interrupt vector as shown in Figure 12−15. The TBCCR0 CCIFG
flag is automatically reset when the TBCCR0 interrupt request is serviced.
Figure 12−15. Capture/Compare TBCCR0 Interrupt Flag
D
Set
Q
IRQ, Interrupt Service Requested
Reset
Timer Clock
POR
CAP
EQU0
Capture
IRACC, Interrupt Request Accepted
CCIE
TBIV, Interrupt Vector Generator
The TBIFG flag and TBCCRx CCIFG flags (excluding TBCCR0 CCIFG) are
prioritized and combined to source a single interrupt vector. The interrupt
vector register TBIV is used to determine which flag requested an interrupt.
The highest priority enabled interrupt (excluding TBCCR0 CCIFG) generates
a number in the TBIV register (see register description). This number can be
evaluated or added to the program counter to automatically enter the
appropriate software routine. Disabled Timer_B interrupts do not affect the
TBIV value.
Any access, read or write, of the TBIV register automatically resets the highest
pending interrupt flag. If another interrupt flag is set, another interrupt is
immediately generated after servicing the initial interrupt. For example, if the
TBCCR1 and TBCCR2 CCIFG flags are set when the interrupt service routine
accesses the TBIV register, TBCCR1 CCIFG is reset automatically. After the
RETI instruction of the interrupt service routine is executed, the TBCCR2
CCIFG flag will generate another interrupt.