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SVS Operation
6-5
Supply Voltage Supervisor
6.2.3 Changing the VLDx Bits
When the VLDx bits are changed, two settling delays are implemented to
allows the SVS circuitry to settle. During each delay, the SVS will not set
SVSFG. The delays, t
d(SVSon)
and t
settle,
are shown in Figure 6−2. The
t
d(SVSon)
delay takes affect when VLDx is changed from zero to any non-zero
value and is a approximately 50 µs. The t
settle
delay takes affect when the
VLDx bits change from any non-zero value to any other non-zero value and
is a maximum of ~12 µs. See the device-specific datasheet for the delay
parameters.
During the delays, the SVS will not flag a low-voltage condition or reset the
device, and the SVSON bit is cleared. Software can test the SVSON bit to
determine when the delay has elapsed and the SVS is monitoring the voltage
properly.
Figure 6−2. SVSON state When Changing VLDx
01 2 1523
VLD vs Time
0
1
0
1
2
3
4
14
15
VLDx
SVSON
t
settle
t
settle
t
settle
t
d(SVSon)