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Timer_A Registers
11-20
Timer_A
TACTL, Timer_A Control Register
15 14 13 12 11 10 9 8
Unused TASSELx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
76543210
IDx MCx Unused TACLR TAIE TAIFG
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) w−(0) rw−(0) rw−(0)
Unused
Bits
15-10
Unused
TASSELx
Bits
9-8
Timer_A clock source select
00 TACLK
01 ACLK
10 SMCLK
11 INCLK
IDx
Bits
7-6
Input divider. These bits select the divider for the input clock.
00 /1
01 /2
10 /4
11 /8
MCx
Bits
5-4
Mode control. Setting MCx = 00h when Timer_A is not in use conserves
power.
00 Stop mode: the timer is halted
01 Up mode: the timer counts up to TACCR0
10 Continuous mode: the timer counts up to 0FFFFh
11 Up/down mode: the timer counts up to TACCR0 then down to 0000h
Unused
Bit 3 Unused
TACLR
Bit 2 Timer_A clear. Setting this bit resets TAR, the TACLK divider, and the count
direction. The TACLR bit is automatically reset and is always read as zero.
TAIE
Bit 1 Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
0 Interrupt disabled
1 Interrupt enabled
TAIFG
Bit 0 Timer_A interrupt flag
0 No interrupt pending
1 Interrupt pending