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Instruction Set
3-27
RISC 16−Bit CPU
BIT[.W] Test bits in destination
BIT.B Test bits in destination
Syntax BIT src,dst or BIT.W src,dst
Operation src .AND. dst
Description The source and destination operands are logically ANDed. The result affects
only the status bits. The source and destination operands are not affected.
Status Bits N: Set if MSB of result is set, reset otherwise
Z: Set if result is zero, reset otherwise
C: Set if result is not zero, reset otherwise (.NOT. Zero)
V: Reset
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example If bit 9 of R8 is set, a branch is taken to label TOM.
BIT #0200h,R8 ; bit 9 of R8 set?
JNZ TOM ; Yes, branch to TOM
... ; No, proceed
Example If bit 3 of R8 is set, a branch is taken to label TOM.
BIT.B #8,R8
JC TOM
Example A serial communication receive bit (RCV) is tested. Because the carry bit is
equal to the state of the tested bit while using the BIT instruction to test a single
bit, the carry bit is used by the subsequent instruction; the read information is
shifted into register RECBUF.
;
; Serial communication with LSB is shifted first:
; xxxx xxxx xxxx xxxx
BIT.B #RCV,RCCTL ; Bit info into carry
RRC RECBUF ; Carry −> MSB of RECBUF
; cxxx xxxx
...... ; repeat previous two instructions
...... ; 8 times
; cccc cccc
; ^ ^
; MSB LSB
; Serial communication with MSB shifted first:
BIT.B #RCV,RCCTL ; Bit info into carry
RLC.B RECBUF ; Carry −> LSB of RECBUF
; xxxx xxxc
...... ; repeat previous two instructions
...... ; 8 times
; cccc cccc
; | LSB
; MSB