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Command Dictionary Analyze Drc Violation
FastScan and FlexTest Reference Manual, V8.6_4
2-133
C3 | C4 — The netlist contains all gates between the source cell and the
failing cell, the failing clock and the failing cell, and the failing clock and
the source cell. The pin data shows the clock cone data for the failing clock.
C5/C6 — The netlist contains all gates between the failing clock and the
failing cell. The pin data shows the clock cone data for the failing clock.
C7 — The netlist contains all the gates in the backtrace cone of the bad
clock input of the failing cell. The pin data shows the constrained values.
C8 | C9 — The netlist contains all the gates in the backtrace cone of the
failing primary output. The pin data shows the clock cone data for the
failing clock.
The following lists the Data rules violation IDs. For a complete description of
these violations refer to the “Scan Cell Data Rules” section of the Design-for-
Test: Common Resources Manual.
D1 — The netlist contains all the gates in the backtrace cone of the clock
inputs of the disturbed scan cell. The pin data shows the pattern values the
tool simulated when it encountered the error.
D2 — The netlist contains all the gates in the backtrace cone of the failing
gate. The pin data shows the values the tool simulated for all time periods
of the shift procedure.
D3 — The netlist contains all the gates in the backtrace cone of the failing
gate. The pin data shows the values the tool simulates for all time periods of
the master_observe procedure.
D4 — The netlist contains all the gates in the backtrace cone of the failing
gate. The pin data shows the values the tool simulates for all time periods of
the skew_load procedure.
D5 — The netlist contains the disturbed gate, and there is no pin data.
D6 | D7 | D8 — The netlist contains all the gates in the backtrace cone of
the clock inputs of the failing gate. The pin data shows the value that the
tool simulates when all clocks are at their off-states.
D9 — The netlist contains all the gates in the backtrace cone of the clock
inputs of the failing gate. The pin data shows the pattern value the tool
simulated when it encountered the error.