Filter
Top Products
FastScan and FlexTest Reference Manual, V8.6_4
2-406
Save Patterns Command Dictionary
heading “Arguments”. When saving your patterns using the Save Patterns
command, choose the format_switch that best suits your needs.
The tool by default pads excess load and unload values with Xs. You can override
the default by specifying the -Nopadding.
The module name created for the Verilog and VHDL testbenches, using enhanced
AVI outputs via the -PROcfile switch, is determined by the file name specified on
the Save Patterns command line. The module name consists of the design name,
followed by an underscore, followed by the file name (minus any path names),
followed by “_ctl”. Additionally, any periods (“.”) in the filename are converted
to underscores (“_”). This allows you to change the module name in the testbench
by simply changing the name of the file on the Save Patterns command line. See
the Examples section of this command for an example of the module name in the
testbench that the tool creates.
By default, when you are not using the -Procfile switch, the module name created
consists of the design name followed by “_ctl”.
Arguments
• filename
A required string that specifies the name of the file to which you want to write
the test pattern set.
• -Replace
An optional switch that specifies replacement of the contents of filename, if a
file by that name already exists.
• format_switch
An optional switch that specifies the format in which you want to save the test
pattern set. The formats divide into three groups. The first group lists the
general purpose formats. The second group lists the simulation and test
formats. The third group lists the ASIC vendor formats.
The general purpose format switch choices are as follows:
-
Ascii — A switch that writes the patterns in the standard ASCII format.
The ASCII format includes the statistics report, environment settings, scan
structure definition, scan chain functional test, scan test patterns, and the
scan cell information. This is the command’s default.