Toshiba TLCS-900 Computer Hardware User Manual


 
TMP92CM22
2007-02-16
92CM22-101
Figure 3.7.2 TMRA23 Block Diagram
φT1
φT16
φT256
8-bit comparator
register (CP3)
8-bit comparator
(CP2)
8-bit up counter
(UC2)
2
n
over-
flow
8-bit up counter
(UC3)
Timer
flip-flop
TA3FF
Match
detect
Match
detect
8-bit timer
register TA3REG
φT1
φT4
φT16
512 256 128 64 32 16 8 4 2
φT1 φT4 φT16 φT256
Run/clea
r
Prescale
r
TA23MOD
<TA2CLK1:0>
Prescale
r
clock: φT0
TA23RUN<TA2RUN>
Selecto
r
8-bit timer register
TA2REG
TA23MOD
<PWM21:20>
TA23MOD
<TA23M1:0>
TMRA2
interrupt output:
INTTA2
TMRA2
match output:
TA2TRG
TA23MOD
<TA3CLK1:0>
TA23RUN<TA3RUN>
TA3FFCR
Timer flip-flop
output:
TA3OUT
TMRA3
interrupt outptu:
INTTA3
Internal data bus
TA23RUN
<TA2RDE>
TA23RUN
<TA23PRUN>
Selecto
r
Internal data bus
TA2TRG
Register buffer 2