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TMP92CM22
2007-02-16
92CM22-235
(2) Interrupt control (1/2)
Symbol Name Address 7 6 5 4 3 2 1 0
INT2 INT1
I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTE12
INT1 & INT2
enable
00D0H
1: INT2
Interrupt request level. 1: INT1 Interrupt request level
− INT3
− − − − I3C I3M2 I3M1 I3M0
− − − − R R/W
0 0 0 0 0 0 0 0
INTE3
INT3
enable
00D1H
Always write “0”. 1: INT3 Interrupt request level
INTTA1 (TMRA1) INTTA0 (TMRA0)
ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C ITA0M2 ITA0M1 ITA0M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTETA01
INTTA0 &
INTTA1
enable
00D4H
1: INTTA1
Interrupt request level 1: INTTA0 Interrupt request level
INTTA3 (TMRA3) INTTA2 (TMRA2)
ITA3C ITA3M2 ITA3M1 ITA3M0 ITA2C ITA2M2 ITA2M1 ITA2M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTETA23
INTTA2 &
INTTA3
enable
00D5H
1: INTTA3
Interrupt request level 1: INTTA2 Interrupt request level
INTTB1 (TMRB0) INTTB0 (TMRB0)
ITB1C ITB1M2 ITB1M1 ITB1M0 ITB0C ITB0M2 ITB0M1 ITB0M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTETB01
INTTB00 &
INTTB01
enable
00D8H
1: INTTB1
Interrupt request level 1: INTTB0 Interrupt request level
− INTTBO0 (TMRB0)
− − − − ITBO0C ITBO0M2 ITBO0M1 ITBO0M0
R R/W R R/W
0 0 0 0 0 0 0
INTETBO0
INTTBO0
(Overflow)
enable
00DAH
Always write “0”. 1: INTTBO0 Interrupt request level
INTTX0 INTRX0
ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTES0
INTRX0 &
INTTX0
enable
00DBH
1: INTTX0
Interrupt request level 1: INTRX0 Interrupt request level
INTTX1 INTRX1
ITX1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTES1
INTRX1 &
INTTX1
enable
00DCH
1: INTTX1
Interrupt request level 1: INTRX1 Interrupt request level
INT5 INT4
I5C I5M2 I5M1 I5M0 I4C I4M2 I4M1 I4M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTE45
INT4 & INT5
enable
00E0H
1: INT5
Interrupt request level 1: INT4 Interrupt request level
INTTB11 (TMRB1) INTTB10 (TMRB1)
ITB11C ITB11M2 ITB11M1 ITB11M0 ITB10C ITB10M2 ITB10M1 ITB10M0
R R/W R R/W
0 0 0 0 0 0 0 0
INTETB1
INTB10 &
INTTB11
enable
00E1H
1: INTTB11
Interrupt request level 1: INTTB10 Interrupt request level
− INTTBO1 (TMRB1)
− − − − ITBO1C ITBO1M2 ITBO1M1 ITBO1M0
− − − − R R/W
INTETBO1
INTTBO1
(Overflow)
enable
00E2H
Always write “0”. 0 0 0 0
− INTSBE0
− − − − ISBE0C ISBE0M2 ISBE0M1 ISBE0M0
− − − − R R/W
− − − − 0 0 0 0
INTESB0
INTSBE0
enable
00E3H
Always write “0”.
1: INTSBE0 Interrupt request level