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TMP92CM22
2007-02-16
92CM22-127
3.8.3 SFRs
TMRB0 Run Register
7 6 5 4 3 2 1 0
Bit symbol TB0RDE − I2TB0 TB0PRUN TB0RUNTB0RUN
(1180H)
Read/Write R/W R/W R/W
After reset 0 0 0 0 0
TMRB0
Prescaler
Up counter
UC10
Function Double
buffer
0: Disable
1: Enable
Always
write “0”.
IDLE2
0: Stop
1: Operate
0: Stop and clear
1: Run (Count)
0 Stop and clear
1 Count
Note: The values of bits 1, 4, and 5 of TB0RUN are undefined when read.
TMRB1 Run Register
7 6 5 4 3 2 1 0
Bit symbol TB1RDE − I2TB1 TB1PRUN TB1RUNTB1RUN
(1190H)
Read/Write R/W R/W R/W
After reset 0 0 0 0 0
TMRB1
Prescaler
Up counter
UC12
Function Double
buffer
0: Disable
1: Enable
Always
write “0”.
IDLE2
0: Stop
1: Operate
0: Stop and clear
1: Run (Count)
0 Stop and clear
1 Count
Note: The values of bits 1, 4, and 5 of TB1RUN are undefined when read.
Figure 3.8.3 Register for TMRB
Count operation
Count operation